DS90LV032A 3V LVDS Quad CMOS Differential Line Receiver
• >400 Mbps (200 MHz) switching rates
• 0.1 ns channel-to-channel skew (typical)
• 0.1 ns differential skew (typical)
• 3.3 ns maximum propagation delay
• 3.3V power supply design (LVDS) technology.
• Power down high impedance on LVDS inputs
• Low Power design (40mW @ 3.3V static)
• Interoperable with existing 5V LVDS networks
• Accepts small swing (350 mV typical) VID
• Supports open, short and terminated input fail-safe
• Compatible with ANSI/TIA/EIA-644
